A typical display system generally uses a processor to transmit image information in parallel to a display device. In one common display system, red (R), green (G) and blue (B), also referred to as RGB, information relating to each pixel is sent to the display in parallel, along with a clock signal and both horizontal (Hsync) and vertical (Vsync) synchronization signals.
However, difficulties arise when attempting to test such a display system when no processor is available. Typically, a pattern generator is supplied with the user RGB data, along with the horizontal and vertical synchronization signals and the clock signal, and then generates the parallel image data. However, it is becoming increasingly desirable to reduce power consumption and the number of pins associated with this type of data transmission. This desire has given rise to the use of a packet-based serial data transmission methodology for delivering display data to a display system. Unfortunately, converting the parallel image data to a serial data stream requires precise timing and clocking signals. When the parallel data is being converted to serial data for transmission in a packet-based system, the system “overhead” must be considered. For example, when the data is formatted for a packet-based system, header, and error correction/detection mechanisms are added to the image data. The transmission time for this overhead data needs to be considered when transmitting the image data to the display.
Therefore, it is desirable to have a simple and accurate way to convert parallel image data to a serial bit stream, while retaining proper signal timing and display information.